GDC21D601 Datasheet, PDF (53/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

Section 8. Power Management Unit
1. General Description
The PMU block provides:
• Clock distribution of all over system
• Reset, RUN and Power down modes control
Figure 1. shows the PMU Block Diagram.
nPOR
WD_OF_IN
MAN_RESET_IN
P_A[7:0]
P_D[15:0]
P_SEL
P_STB
P_WRITE
INT_REQ_IN
tfclk
tbclk
SCLK_IN
PCLK_IN
SPCLK
Reset
Debounce
Digital Filter
PMU
Registers
BCLK
Freq.
Control
PCLK
Freq.
Control
Reset
Control
PMU
Control
FCLK, BCLK
Distribution
Control
PCLK
Distribution
Control
GDC21D601
B_RESETn_OUT
P_RESETn0_OUT
P_RESETn1_OUT
RESETn_EXT
WD_OF_OUT
nPDM
FASTBUS
REMAP
FCLK
BCLK_XXX for ASB block
BCLK_XXX for Peripherals
PCLK_XXXX for Peripherals
Figure 1. PMU Block Diagram
54