GDC21D601 Datasheet, PDF (159/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
3.4 Transfer Number Register 0, 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TNB15 TNB14 TNB13 TNB12 TNB11 TNB10 TNB9 TNB8 TNB7 TNB6 TNB5 TNB4 TNB3 TNB2 TNB1 TNB0
Figure 4. Transfer Number Register
3.5 Channel Control Register 0, 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Bit 15 14~12 11 10
9
8
7
6-5 4 3
2
10
DRAMAcc ACKLEN DADRM SADRM TSIZE1 TSIZE0 REV. RTYPE[1:0] AREQ TBUSM TENDFL INTREN CHEN
Figure 5. Channel Control Register
BIT
15
14 ~ 12
11
10
9~8
6~5
4
3
2
1
0
Others
INIT.
VALUE
0
000
0
0
00
00
0
0
0
0
0
0
Table 3. Channel Control Register
NAME
DRAMAcc
ACKLEN
DADRM
SADRM
TSIZE[1:0]
RTYPE[1:0]
ATREQ
TBUSM
TENDFL
INTREN
CHEN
DESCRIPTION
Indicate to the DRAM Controller during DMA transfer
0 : not DRAM access 1 : DRAM access
Enlarge the LOW phase of the DMAck signal for single address
transfer
Destination addressing mode
0 : fixed addressing
1 : incremental addressing
Source addressing mode
0 : fixed addressing
1 : incremental addressing
Transfer size
00 : Byte 01 : Half-word 10 : Word 11 : Reserved
DMA request resource selecting
00 : Memory space to Memory space
01 : Memory space to External IO Device
10 : External IO Device to Memory space
Others : Reserved
Auto request enable
Transfer bus mode
0 : Burst
1 : cycle-steal mode
Transfer end flag
0 : incomplete transfer 1 : complete transfer
Write 1 to clear this flag bit
DMA transfer complete interrupt enable
0 : interrupt disable 1 : interrupt enable
Channel mode
0 : channel disable
1 : channel enable
Reserved
160