GDC21D601 Datasheet, PDF (181/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

Interrupt Controller Register (@0xFFFF F200)
ABBREVIATION
INTC
INTMD
INTPOL
ADDRESS
0xFFFFF200
0xFFFFF204
0xFFFFF208
DESCRIPTIONS
Interrupt Control/Mask Register
INT25 : SWI(Software Interrupt)
INT24 : Timer 5
INT23 : Timer 4
INT22 : Timer 3
INT21 : Timer 2
INT20 : Timer 1
INT19 : Timer 0
INT18 : SSPI 1
INT17 : SSPI 0
INT16 : Smart Card Interface
INT15 : UART 1
INT14 : UART 0
INT13 : I²C 2
INT12 : I²C 1
INT11 : I²C 0
INT10: WDT(Watchdog Timer)
INT9 : RTC(Real Time Clock)
INT8 : DMA(Direct Memory Access)
INT7 : COM RX
INT6 : COM TX
INT5 : External Interrupt 5
INT4 : External Interrupt 4
INT3 : External Interrupt 3
INT2 : External Interrupt 2
INT1 : External Interrupt 1
INT0 : External Interrupt 0
Interrupt Trigger Mode control
Interrupt Trigger Polarity control Register.
Mode
0
0
1
1
Polarity
0
1
0
1
Triggered by
Falling Edge
Rising Edge
Low Level
High Level
GDC21D601
R/W INITIAL VALUE
R/W 26h’3FFFFFF
R/W 26h’2000000
R/W 26h’2000000
INTDIR
INTFIQS
INTIRQS
INTFIQMSK
INTIRQMSK
INTSCL
INTTICIN
INTTICOUT
0xFFFFF20C
0xFFFFF210
0xFFFFF214
0xFFFFF218
0xFFFFF21C
0xFFFFF220
0xFFFFF240
0xFFFFF280
Interrupt direction control Register
(0 / 1 = Request IRQ / FIQ)
FIQ Status Flag Register ( 0/1 = Clear/Set)
IRQ Status Flag Register( 0/1 = Clear/Set)
FIQ Mask Register( 0/1 = Clear/Masked)
IRQ Mask Register( 0/1 = Clear/Masked)
Interrupt Status Clear Register
0 / 1 = Clear / Set
TIC Input Register
TIC Output Register
R/W 26h’0000000
R 26h’0000000
R 26h’0000000
R/W 26h’0000000
R/W 26h’0000000
W 26h’0000000
R/W
0x00
R/W
0x00
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