GDC21D601 Datasheet, PDF (125/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
3. Signal Description
The GDC21D601 UART module is connected to the APB bus.
Table 1. Signal Descriptions
NAME
U_CLK
Type
I
nB_RES0
I
P_A[2:0]
I
P_D[7:0] I/O
P_STB
I
P_WRITE I
P_SEL
I
INT_UART O
NCTS
I
SOURCE/
DESTINATION
CPG
PMU
APB Bridge
APB Bridge
APB Bridge
APB Bridge
APB Bridge
INTC
External
DESCRIPTION
UART external Clock input
This connects the main timing reference to the UART.
3.6864Mhz is recommendable input clock frequency.
Reset signal generated from the APB Bridge(Master Reset)
When this input is low, it clears all the registers (except the Receiver
Buffer, Transmitter Holding, and Divisor Latches) and the control logic
of the UART. The states of various output signals (SOUT, INT_UART,
nRTS, nDTR) are affected by an active nB_RES[0] input.
Register select. Address signals connected to these 3 inputs select a
UART register for the CPU to read from or write to during data transfer.
A table of registers and their addresses is shown below. Note that the
state of the Divisor Latches
Data Bus. This bus comprises eight TRI-STATE input/output lines.
The bus provides bi-directional communications between the UART and
the CPU. Data, control words and status information are transferred via
the P_D[7:0] data bus.
This strobe signal is used to time all accesses on the peripheral bus. The
falling edge of P_STB is coincident with the falling edge of
B_CLK.(ASB System Clock)
When this signal is HIGH, it indicates a write to a peripheral. When this
signal is LOW, it indicates a read from a peripheral. This signal has the
same timing as the peripheral address bus. It becomes valid before
P_STB goes to HIGH and remains valid after P_STB goes to LOW.
When this signal is HIGH, it indicates that this module has been selected
by the APB bridge. This selection is a decode of the system address bus
(ASB).
Interrupt. This pin goes to high whenever any one of the following
interrupt types has an active high condition and is enabled via EIR:
Receiver Error Flag; Received Data Available:timeout(FIFO Mode
only); Transmitter Holding Register Empty; and MODEM Status. The
INT_UART signal is reset to low upon the appropriate interrupt service
or a Master Reset operation.
Clear to Send. When this signal is low, it indicates that the MODEM or
data set is ready to exchange data. The NCTS signal is a MODEM status
input whose conditions can be tested by the CPU reading bit 4 (CTS) of
the MODEM Status Register indicates whether the NCTS input has
changed its state since the previous reading of the MODEM Status
Register. NCTS has no effect on the Transmitter.
** Note : Whenever the CTS bit of the MODEM Status Register
changes its state, an interrupt is generated if the MODEM Status
interrupt is enabled.
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