GDC21D601 Datasheet, PDF (60/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
4.7 PCLK Frequency Control Register
This register is used to selecting the frequency of PCLK in the APB at RUN mode. Default value is 0000. The
address of access the register is PMU_BASE + 0x14h
Table 11. CLKMODE Bit Functions
BIT
INITIAL
NAME
FUNCTION
2-0
000
PCLKCR
Select the PCLK source
000 – PCLK is external PCLK source
001 – PCLK is the SCLK divided by 2
010 – PCLK is the SCLK divided by 4
011 – PCLK is the SCLK divided by 8
100 – PCLK is the SCLK divided by 16
101 – PCLK is the SCLK divided by 32
110 – PCLK is the SCLK divided by 64
111 – PCLK is the SCLK divided by 128
4.8 Reset Control Register
This register is used for generating the S/W reset operation. The MCU is entered in reset state, when this register is
set to high, it is cleared automatically at the end of manual reset procedure. The address is PMU_BASE + 0x30h.
Table 12. RSTCR Bit Functions
BIT
INITIAL
NAME
FUNCTION
0
0
RSTCR
Manual reset control bits
0 - Normal , 1 - manual reset
4.9 Test Control Register
TSTCR controls the normal mode, PMU test mode or the TIC test mode. The address is PMU_BASE + 0x40h.
Table 13. TSTCR Bit Functions
BIT
INITIAL
NAME
FUNCTION
1
0
TSTCR
0 – Normal operation mode
1 – TIC Test mode
0
0
0 – Normal operation mode
1 – PMU test mode
61