GDC21D601 Datasheet, PDF (164/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
4.2 Single Address Mode
The single address mode of DMAC are described in the Figure 12. In single address mode, there are two types of
transfer, one is memory-to-I/O device that source is memory area and destination is external I/O device, and the
other is external I/O device–to-memory that source is I/O device and destination is memory area. Single address
transfer mode is composed of only one data transaction, so it is very fast to transfer the data comparing with dual
addres mode in which composed of 2 transactions : read transaction and write transactio. The I/O device is acessed
by nDREQ and nDACK signals. nDACK signals are controlled by the ACKLEN field in CCR. And nDACK
signals are coincident with the RAS and CAS signals from DRAM Controller. When memory is DRAM, you must
set properly the control flags in the control register in DRAM Controller and DMA Controller.
The example of the register setting for memory-to-I/O device transfer in single address mode is following that : 1)
set Source Address Register (SAR). In this register you write the source area address. 2) set Destination Address
Register (DAR). In this register you write the destination area address. 3) set Transfer Number Register (TNR). In
this register you write the transfer number value. 4) set Channel Control Register (CCR). In this register you
should write properly the control value. When data transfer is the memory space to external I/O devices,
RTYPE[1:0] field value are should be “01”, and DARAM field is should be “0”, and SADRM fields should be “1”.
You should set the TSIZE[1:0] field properly by the transferred data width. And you must set the CHEN field to
“1”. INTREN field are set by your need. 5) finally set DMAEN field to “1” in DMA Operation Register
(DMAOR). If you set AutoReq field in CCR, as soon as set DMAEN field, DMA transfer the data.
Figure 13 shows the timing diagram of the memory-to-I/O device transfer when CCR value is 0x0523. Figure 14
shows the timing diagram of the timing diagram of the I/O device-to-memory transfer when CCR value is 0x0943.
In these case the contents of the control register for DRAM in DRAM Controller is 0x69. In the end of DMA
transfer, DMA Controller is initialized by clearing the TENDFL field in CCR. This can be performed by writing
“1” value in this field.
DMAC
TEMP
Internal of MCU
Address/Control
Internal / External
Memory Space
Data
nDACK
nDREQ
Internal / External
I/O Module
Figure 12. DMAC Single Address Mode Block Diagram
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