GDC21D601 Datasheet, PDF (38/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
2. Signal Description
The Static Memory Controller module is connected to the ASB bus. In Table 1. Static Memory Controller ASB
signal descriptions show the internal bus interface signals(AMBA signals) to the Static Memory Controller
NAME
BA[26:24, 4:0]
BCLK
BD[31:0]
BERROR
BLAST
BWAIT
BnRES
BSIZE[1:0]
BTRAN[1:0]
BWRITE
DSELSRAM
DSELREG
Table 1. Static Memory Controller ASB Signal Descriptions
TYPE
I
I
I/O
O
O
O
I
I
I
I
I
I
DESCRIPTION
System address bus. The SRAM controller only requires seven bits of this bus
to do the necessary encoding/decoding.
The ASB clock.
Bi-directional system data bus. The data bus is driven by this block during read
transfers from configuration registers only.
LOW during phase one of BCLK when the Static Memory Controller is
selected.
LOW during phase one of BCLK when the Static Memory Controller is
selected.
This slave response is driven during phase one of BCLK when the Static
Memory Controller is selected and is used to indicate if the memory has
completed its current transfer.
The reset status of the ASB.
The size of the transfer data which may be byte, half-word, or word.
These signals are used to determine sequential and non-sequential accesses.
When this signal is HIGH, it indicates a write transfer and when LOW a read.
When this signal is HIGH, it indicates that the Static Memory Controller is
selected.
When HIGH, this signal indicates that one of the Bank Configuration registers
is selected.
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