GDC21D601 Datasheet, PDF (72/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
The Interval Timer Mode
To use the WDT as an interval timer, clear WT/nIT to 0 and set TMEN to 1. A watchdog timer interrupt
(INT_WDT) is generated each time the timer counter overflows. This function can be used to generate interval
timer interrupts at regular intervals.
TCNT
value
OxFF
WT/nIT = 0
Ox00
TMEN = 1
ITOVF = 1
WDTINT generated
time
Figure 5. Operation in the Interval Timer Mode
4.1 Timing of Setting and Clearing the Overflow Flag
Timing of setting the overflow flag
In the interval timer mode when the TCNT overflows, the ITOVF flag is set to 1 and an watchdog timer interrupt
(INT_WDT) is requested.
In the watchdog timer mode when the TCNT overflows, the WTOVF bit of the SR is set to 1 and a WDTOUT
signal is output. When RSTEN bit is set to 1, TCNT overflow enables an internal reset signal to be generated for
the entire chip.
Timing of clearing the overflow flag
When the Reset Status Register (RSTSR) is read, the overflow flag is cleared.
73