GDC21D601 Datasheet, PDF (131/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Line Control Register
The system programmer specifies the format of the asynchronous data communications exchange and set the
Divisor Latch Access bit via the Line Control Register (LCR). The programmer can also read the contents of the
Line Control Register. The read capability simplifies the system programming and eliminates the need for separate
storage in system memory of the line characteristics. Table 5. Summary of Registers shows the contents of the
LCR. Details on each bit are :
Bit 0 and 1 : These two bits specify the number of bits in each transmitted and received serial character. The
encoding of bits 0 and 1 is as follows:
BIT 1
0
0
1
1
Table 6. Line Control Register Encoding
BIT 0
0
1
0
1
CHARACTER LENGTH
5 Bits
6 Bits
7 Bits
8 Bits
Bit 2 :
This bit specifies the number of Stop bits transmitted and received in each serial character. If bit 2 is a
logic 0, one Stop bit is generated in the transmitted data. If bit 2 is a logic 1 when a 5-bit word length is
selected via bits 0 and 1, One and a half Stop bits are generated. If bit 2 is a logic 1 when either a 6-, 7-,
or 8-bit word length is selected, two Stop bits are generated. The Receiver checks the first Stop-bit only,
regardless of the number of selected Stop bits.
Bit 3 :
This bit is the Parity Enable bit. When bit 3 is a logic 1, a Parity bit is generated (transmit data) or
checked (receive data) between the last data word bit and Stop bit of the serial data. (The Parity bit is
used to produce an even or odd number of 1s when the data word bits and the Parity bit are summed.)
Bit 4 :
This bit is the Even Parity Select bit. When bit 3 is a logic 1 and bit 4 is a logic 0, an odd number of
logic 1s is transmitted or checked in the data word bits and Parity bit. When bit 3 is a logic 1 and bit 4 is
a logic 1, an even number of logic 1s is transmitted or checked.
Bit 5 :
This bit is the Stick Parity bit. When bits 3, 4, and 5 are logic 1, the Parity bit is transmitted and checked
as a logic 0. If bits 3 and 5 are 1 and bit 4 is a logic 0, then the Parity bit is transmitted and checked as a
logic 1. If bit 5 is a logic 0 Stick Parity is disabled.
Bit 6 :
This bit is the Break Control bit. It causes a break condition to be transmitted to the receiving UART.
When it is set to a logic 1, the serial output (SOUT) is forced to be the Spacing (logic 0) state. The break
is disabled by setting bit 6 to a logic 0. The Break Control bit acts only on SOUT and has no effect on
the transmitter logic.
** Note : This feature enables the CPU to alert a terminal in a computer communications system. If the
following sequence is followed, no erroneous or extraneous characters will be transmitted because of the
break.
Bit 7 :
This bit is the Divisor Latch Access Bit (DLAB), It must be set to high (logic 1) to access the Divisor
Latches of the Baud Generator during a Read or Write operation. It must be set to low (logic 0) to access
the Receiver Buffer, the Transmitter Holding Register, or the Interrupt Enable Register.
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