GDC21D601 Datasheet, PDF (172/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

DRAM Controller Registers(@0xFFFFED00) -- Continued
ABBREVIATION
DRAMTCR
ADDRESS
0xFFFFED0C
DESCRIPTIONS
DRAM Test Control Register
Bit 15-4: Reserved
Bit 3: TESTINC(Test Increment)
Column address auto increment
0 / 1 = Disabled / Enabled
Bit 2: FORCEADV
Forces refresh counter by BCLK
0 / 1 = Disabled / Enabled
Bit 1-0: Force size
00 : byte
01 : Half-word
10 : Word (Default)
11 : Reserved
GDC21D601
R/W INITIAL VALUE
W
4b’0010
173