GDC21D601 Datasheet, PDF (34/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
4.3 DRAM Control Register for CPU (DRAMConCPU)
This Register controls the DRAM control signals when DRAM accessed by CPU. In normal condition, the
DRAM access time is changed by the bus master is CPU or DMA Controller. In case of bus master is DMA
Controller, the transfer timing should be properly set to the external I/O device and DRAM, so for the optimal
system performance the DRAM access by the CPU is set in this DRAM Control Register for CPU
(DRAMConCPU) and in case of the DRAM access by the DMA Controller DRAM control signals are controlled
by the DRAM Control Register for DMA (DRAMConDMA).
15
7
6
5
Reserved
DMAEn
TRP
4
3
2
1
0
TCP
WaitCnt
BankSize
Figure 8. DRAM Control Register for CPU (DRAMConCPU)
DMAEn
If DMA transfer, then the DRAM control signals are controlled by DRAM Control Register for DMA
(DRAMDonDMA) by this bit setting. When this bit is ‘0’, then the DRAM control signals are
controlled by bit fields in this Control Register (DRAMConCPU) during DRAM access.
TRP
Control the timing of difference between the RAS and CAS signal by this bit field setting. When this
bit is ‘0’, then DRAM access are absolutely no wait, so DRAM access time is very short, but should
be considered the operating frequency of the MCU and DRAM access time.
TCP
Control the timing of the Low phase of CAS signals. When this bit is ‘1’, then the Low phase of the
CAS signals are enlarged to one cycle of BCLK. When this bit is ‘0’, then the Low phase of the CAS
signals are half clock of BCLK.
WaitCnt This bit fields control the DRAM access time. The wait state is inserted in ASB BUS by the value of
these WaitCnt fields. (00=0-wait, 01=1-wait, 10=2-wait, 11=3-wait)
BankSize These bits indicate the data width of the DRAM Bank. The data width of the DRAM by BankSize are
shown Table 6.
Table 6. Data width of the DRAM by BankSize[1:0] fields
BankSize[1:0]
00
01
10
11
Data Width of DRAM
Byte
Half Word
Word
Reserved
35