GDC21D601 Datasheet, PDF (147/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
5.2 Register Memory Map
The base address of the SMART CARD interface is 0xFFFFF700 and the offset of any particular register from the
base address is determined.
ADDRESS
SMART CARD
I/F Base
SMART CARD
I/F Base + 0b0001
SMART CARD
I/F Base + 0b0010
SMART CARD
I/F Base + 0b0011
SMART CARD
I/F Base + 0b0101
SMART CARD
I/F Base + 0b0111
SMART CARD
I/F Base + 0b1000
SMART CARD
I/F Base + 0b1001
SMART CARD
I/F Base + 0b1010
SMART CARD
I/F Base + 0b1011
SMART CARD
I/F Base + 0b1100
SMART CARD
I/F Base + 0b1101
Table 9. SMART CARD Interface Register Memory Map
REGISTER
RBR/THR (DLAB = 0)
DLL (DLAB = 1)
IER (DLAB = 0)
DLM (DLAB = 1)
IIR/FCR
READ LOCATION
Receiver Buffer
Divisor Latch (LS)
Interrupt Enable
Divisor Latch (MS)
Interrupt Ident
WRITE LOCATION
Transmitter Holding
Divisor Latch (MS)
Interrupt Enable
Divisor Latch (MS)
FIF Control
LCR
Line Control
Line Control
LSR
Line Status
SCR
Scratch
Scratch
SMCR
Smart card control
Smart card control
SMDLL
Divisor Latch (LS) for SMCLK Divisor Latch (LS) for SMCLK
SMDLM
Divisor Latch (MS) for SMCLK Divisor Latch (MS) for SMCLK
SMSR
Status for SMPED Error
TIR
Test Register for Input
TOR
Test Register for Output
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