GDC21D601 Datasheet, PDF (32/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
3.5 Refresh Control Block
The refresh timer is a 7-bit timer counter which counts down and generates a refresh request when it reaches zero,
at this point it is reloaded with the value in the refresh control register. This allows refresh frequencies from the
Refresh Control Register and BCLK input clock.
3.6 ASB Interface Block
The ASB interface provides the interaction with the main AMBA bus. The DRAM controller will initiate a DRAM
access when the DSELDRAM signal is asserted, or access the control registers when the DSELREG strobe is
asserted. The timing of the ASB transfers is described in detail in the AMBA Specification rev. D. At a 256-word
boundary, the BLAST signal will be asserted to indicate to the bus master that the burst sequence should be broken
within the page boundary.
This block also generates the row and column addresses. During burst mode accesses, the column address is
provided by a 10-bit column address incrementor to provide adequate column address timing.
BCLK
PDREQ
PDACK
nRAS[1:0]
nCAS[3:0]
nOE
nWE
Figure 6. DRAM Signal Timing : Power Down Mode
33