GDC21D601 Datasheet, PDF (174/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Static Memory Controller Registers(@0xFFFF F000) -- Continued
ABBREVIATION
MEMCFG2
MEMCFG3
MEMCFG4
ADDRESS
0xFFFFEC04
0xFFFFEC08
0xFFFFEC0C
DESCRIPTIONS
Memory Configuration Register 2
NCS3 area control
Bit 31-30: Reserved
Bit 29: EXPRDY polarity (0:Active High)
Bit 28: Control signal type
0/1=ARM type / Motorola type
Bit 27: FlashON –Reserved
Bit 26: Expansion clock Enable
Bit 25-24: Mem width
00: 32-bit memory
01: 16-bit memory
10: 8-bit memory
11: Reserved
Bit 23: Burst mode Enable – Reserved
Bit 22-20: Burst wait cycle –Reserved
Bit 19-16: Access wait cycle(1~16cycles)
0000(1 cycle) ~ 1111(16 cycles)
NCS2 area control
Bit 15-14: Reserved
Bit 13: EXPRDY polarity (0:Active High)
Bit 12: Control signal type
0/1=ARM type / Motorola type:
Bit 11: FlashON –Reserved
Bit 10 : Expansion clock Enable
Bit 9-8: Mem width
00: 32-bit memory
01: 16-bit memory
10: 8-bit memory
11: Reserved
Bit 7: Burst mode Enable – Reserved
Bit 6-4: Burst wait cycle –Reserved
Bit 3-0: Access wait cycle(1~16cycles)
0000(1 cycle) ~ 1111(16 cycles)
Memory Configuration Register 3
NCS4,3 area controls
Memory Configuration Register 4
NCS6,5 area controls
R/W INITIAL VALUE
R/W 32’h0000000
0
Default
1 cycle
Default
1 cycle
R/W 32’h0000000
0
R/W 32’h0000000
0
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