GDC21D601 Datasheet, PDF (88/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
(5) FIQ Status Register
Read-only. The FIQ status register is used to reflect the status of all channels set to produce an FIQ interrupt
(IDR(i) = 1). When an interrupt is set for an FIQ occurring, the corresponding bit is set in FIQ status register. The
interrupt handler will examine this register to determine the channel(s) that caused the FIQ interrupt. When the
status clear register is written to ‘1’, the corresponding bit is cleared if that channel is configured to edge trigger
mode. A HIGH bit indicates that the interrupt is active and will generate an interrupt to the processor.
‘1’ : Interrupt Event Occur
‘0’ : No Interrupt Event
Initial value : 0x0000000
25
0
00000000000000000000000000
(6) IRQ Status Register
Read-only. The IRQ status register is used to reflect the status of all channels set to produce an IRQ interrupt
(IDR(i) = 0). When an interrupt is set for an IRQ occurring, the corresponding bit is set in IRQ status register. The
interrupt handler will examine this register to determine the channel(s) that caused the IRQ interrupt. When the
status clear register is written to ‘1’, the corresponding bit is cleared if that channel is configured to edge trigger
mode. A HIGH bit indicates that the interrupt is active and will generate an interrupt to the processor.
‘1’ : Interrupt Event Occur
‘0’ : No Interrupt Event
Initial value : 0x0000000
25
0
00000000000000000000000000
(7) FIQ Mask Register
Readable and Writable. The FIQ request mask register is used to mask the request to generate an interrupt to a
processor. If certain bits within the interrupt controller are not implemented, the corresponding bits in the FIQ
request mask register must be masked. A bit value 0 indicates that the interrupt is unmasked and will allow an
interrupt request to reach the processor. A bit value 1 indicates that the interrupt is masked. On reset, all FIQ
requests are unmasked.
‘1’ : Request Mask
‘0’ : Request Unmask
Initial value : 0x0000000
25
0
00000000000000000000000000
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