GDC21D601 Datasheet, PDF (36/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Section 5. On-Chip SRAM
1. General Description
The GDC21D601 has 8-kbytes of on-chip RAM. The on-chip RAM is linked to the CPU and direct memory access
controller(DMAC) with 32-bit data bus. The CPU and DMA Controller can write data into the on-chip RAM in
byte, half-word, or word units.
2. Signal Description
NAME
BA[31:0]
BD[31:0]
BWAIT
BLAST
BERROR
BWRITE
DSELMEM
BnRES
TYPE
I
I/O
I/O
I/O
I/O
I
I
I
Table 1. Signal Descriptions
DESCRIPTION
System address bus.
Bi-directional system data bus.
LOW during phase one of BCLK.
LOW during phase one of BCLK.
LOW during phase one of BCLK.
When this signal is HIGH, it indicates a write transfer and when LOW a read.
When this signal is HIGH, it indicates that on-chip RAM is selected.
These signals indicate the reset status of the ASB.
3. Function Description
On-Chip SRAM can read data from SRAM and can write data into SRAM in a single clock cycle through ASB bus.
And SRAM is single module which have 32 bit data bus and control lines.
The data in the On-chip RAM can always be accessed in one cycle that make the RAM ideal for use as a program
area, stack area, or data area, which requires high-speed access. The contents of the on-chip RAM are held in both
standby and power-down modes.
Memory area 0x10000000 to 0x10001FFF is allocated to the on-chip RAM as default. When isram signal from
MCU Controller is set to HIGH, memory area 0x00000000 to 0x00001FFF can be allocated to the on-chip RAM.
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