GDC21D601 Datasheet, PDF (27/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
2. Hardware Interface and Signal Description
The DRAM Controller module is connected to the ASB bus. Table 1. DRAM interface ASB signal descriptions
shows the internal bus interface signals to the DRAM controller.
NAME
BA [27:0]
BCLK
BD [7:0]
BERROR
BLAST
BnRES
BSIZE [1:0]
BWAIT
BWRITE
DSELDRAM
DSELREG
Table 1. DRAM Interface ASB Signal Descriptions
DESCRIPTION
System address bus (excluding high order bits).
The ASB clock timing all bus transfers.
Bidirectional system data bus.
Error slave response signal. It is driven to phase 1 if the DRAM controller is selected. This
signal will be asserted, when an access to the DRAM is attempted while the DRAM
controller is in its Power Down mode.
Last transfer of burst slave response signal. It can be driven to phase 1 if the DRAM
controller is selected. It is asserted in order to indicate a 256-word boundary to force a non-
sequential access.
These signals indicate the reset status of the ASB.
These signals indicate the size of the transfer that may be byte, half-word, or word.
Wait slave response signal. It is driven to phase 1 when the DRAM controller is selected. It
is asserted while the DRAM transaction is uncompleted.
When this signal is HIGH, it indicates a write transfer and when LOW a read.
When this signal is HIGH, it indicates that the DRAM is selected.
When this signal is HIGH, it indicates that the DRAM configuration register is selected.
Table 2. DRAM interface External DRAM signal descriptions describes the DRAM controller connections to
external devices of the system and to EBI (External Bus Interface) block .
NAME
nRAS[1:0]
NCAS[3:0]
NDRAMOE
NDRAMWE
nCASFB[3:0]
PDREQ
PDACK
DRAMAMUX
Table 2. External DRAM Signal Descriptions
DESCRIPTION
Active LOW Row Address Strobes, one for each DRAM bank.
Active LOW Column Address Strobes, one for each byte.
Active LOW Output Enable.
Active LOW Write Enable.
This is the nCAS[3:0] signal fed back from the output of the nCAS[3:0] pads.
Power Down Request. This signal indicates that the DRAM controller should enter into its
low-power state, causing the DRAMs to enter into self-refresh state if refresh is enabled.
When it is deasserted, the DRAM controller will exit from low power state.
Power Down Acknowledge. This signal is asserted when the DRAM controller has
successfully entered into its low-power mode. At this point BCLK may be stopped safely. It
is deasserted when the DRAM controller has successfully exited from its low power state.
DRAM Address Multiplex Select. When this signal is HIGH, it indicates to the EBI that the
DRAMA[12:0] address should be used to generate DRAMA[12:0]. This signal provides the
support for a shared EBI, and may not be needed in a system where the DRAM controller
does not share the EBI with other memory controllers. DRAMAMUX is LOW when
DRAM accesses are not performed.
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