GDC21D601 Datasheet, PDF (107/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
7. Examples of Register Setting
7.1 Six Channels
Channel 0 : In free-running counter (Compare match - 0 output at GRB and 1 output at GRA)
Channel 1 : In a periodic counter cleared by GRB ( Compare match - Toggle output at GRA and GRB)
Channel 2 : In a periodic counter cleared by TPB ( Input capture - TPA with both edges, TPB with the falling edge)
Channel 3 : In a periodic counter cleared by GRA ( PWM mode )
Channel 4 : In a periodic counter cleared by GRA ( PWM mode : duty cycle 0% )
Channel 5 : In a periodic counter cleared by GRA ( PWM mode : duty cycle 100%)
# Setting example
RESET
.
.
TSTART = 0xC0;
TCONTR0 = 0x81;
TCONTR1 = 0xC2;
TCONTR2 = 0xC3;
TCONTR3 = 0xA5;
TCONTR4 = 0xCE;
TCONTR5 = 0xBF;
TIER0 = 0xFB;
TIER1 = 0xFA;
TIER2 = 0xFA;
TIER3 = 0xFB;
TIER4 = 0xFB;
TIER5 = 0xFB;
TIOCR0 = 0x9A;
TIOCR1 = 0xBB;
TIOCR2 = 0xDF;
TCOUNT0 = 0xFFF0;
TCOUNT1 = 0xFFF0;
TCOUNT2 = 0x0000;
TCOUNT3 = 0x0000;
TCOUNT4 = 0x0000;
TCOUNT5 = 0x0000;
GRA0 = 0xFFF4;
GRA1 = 0xFFF2;
GRA3 = 0x0A;
GRA4 = 0x04;
GRA5 = 0x0A;
GRB0 = 0xFFFA;
GRB1 = 0xFFF5;
GRB3 = 0x04;
GRB4 = 0x0A;
GRB5 = 0x04;
TPWMR = 0xF8;
TSTARTR = 0xFF;
//internal clock2
//internal clock3
//internal clock4
//external clock2 - rising edge
//external clock3 - falling edge
//external clock4 - both edge
//enable interrupt requests from the MCIA, MCIB
//enable interrupt requests from the MCIA
//enable interrupt requests from the MCIA
//enable interrupt requests from the MCIA, MCIB
//enable interrupt requests from the MCIA, MCIB
//enable interrupt requests from the MCIA, MCIB
.
{Running...}
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