GDC21D601 Datasheet, PDF (37/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Section 6. Static Memory Controller
1. General Description
The Static Memory Controller interfaces the AMBA Advanced System Bus (ASB) to the External Bus Interface
(EBI); controlling the external SRAM, ROM, Flash Memory or off-chip peripherals. Eight separate chip select
banks are provided by this block. Each bank is 256MB in size and can be programmed individually to support:
• 8-, 16- or 32-bit wide, Little-Endian and Big-Endian Memory Format
• variable wait states (up to 16 waits)
• exchangeable active low/high chip select signal (only for CS6 and CS7)
• various type control signal timing
• bus transfers can be extended using the EXPRDY input signal. EXPRDY signal can be used by
exchangeablely active HIGH or LOW in according to control register setting.
Chip PAD
Static Memory Controller
ASB Bus
BCLK
EXPRDY
BnRES
EXPCLK
Main State Machine ^DSELSMI
DSELREG
MODE[1:0]
BTRAN[1:0]
RnW
nWEN[3:0]
Bank Config. Reg.
BWRITE
BSIZE[1:0]
nSRAMOE
nCS[5:0]
CS[7:6]
ASB Interface
&
Chip Select encode
BLAST
BERROR
BWAIT
nWEF[3:0] _{EBI Signal Control}
BA[26:24, 4:0]
BD[31:0]
Aout[23:0]
DataOut[31:0]
DataIn[31:0]
nOutEn[3:0]
Lat mux
Lat ^mux
mux _Lat
BD[31:0]
Figure 1. Static Memory Controller Block Diagram
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