GDC21D601 Datasheet, PDF (31/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
3.4 EBI Control Block
This also generates the control signals required by the EBI(External Bus Interface). The EBI control signals are
divided into three main groups; those related to the control of the Address path, the DataIn path, and the DataOut
path.
Address Path Control
There are three signazls related to the address path of the EBI:
nDRAMALATCH
used to open the address latch of the EBI. This can be used to hold the external address XA
while internal accesses are performed. When this signal is asserted (active LOW) the EBI
address latch should be opened. When a DRAM access is not performed, the DRAM
controller will de-assert this signal. In a shared EBI scheme, other memory
controllers(Static Memory controller,...) must exhibit this behavior when they do not
perform memory accesses.
DRAMAMUX
used to select the DRAMA[12:0] address as the address to be used on XA. This signal will
be asserted (active HIGH) when a DRAM access occurs, and will be de-asserted when the
transfer is completed.
DRAMA[12:0]
the multiplexed row/column address used to access the DRAM.
DataIn and DataOut Path Control
There are four signals related to the data path of the EBI:
nDRAMOUTEN
used to enable the EBIs data drivers onto XData. When this signal is de-asserted (HIGH),
the EBI should disable its drive onto XData. This signal is de-asserted during read cycles
and is asserted at other times. In a shared EBI scheme, other memory controllers must
exhibit this behavior when they do not perform memory accesses.
nDRAMOUTLEN used to latch the value of BD into the EBIs data output latches. When this signal is asserted
(active LOW), the EBI data output latch is opened. This signal will be asserted during
DRAM write transfers, and is de-asserted at other times.
nDRAMINEN
used to enable the EBI data drivers onto BD. When this signal is asserted (active LOW), the
EBI should be driven onto BD. This signal is asserted during DRAM read transfers and is
de-asserted at other times.
nDRAMINLEN[3:0] used to latch the value of XData into the EBI data input latches. When this signal is de-
asserted (HIGH), the EBI data input latch is shut. Four signals are provided to enable
latching of byte / half-word data. nDRAMINLEN[0] is used to latch the data on M_D[7:0].
This signal is normally asserted and will be de-asserted during DRAM read transfers to latch
the current data on XData.
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