GDC21D601 Datasheet, PDF (44/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

4. Programmer’ s Model
4.1 Memory Map
The base address for the Static Memory Controller registers is 0xFFFFEC00
Table 5. Static Memory Controller Memory Map
ADDRESS
SRAMRegBase + 00000
SRAMRegBase + 00004
SRAMRegBase + 00008
SRAMRegBase + 0000C
DESCRIPTION
Memory Configuration Register 1 (MEMCFG1)
Memory Configuration Register 2 (MEMCFG2)
Memory Configuration Register 3 (MEMCFG3)
Memory Configuration Register 4 (MEMCFG4)
GDC21D601
INITIAL VALUE
32’h00000004
32’h00000000
32’h00000000
32’h00000000
4.2 Memory Configuration Registers
31
16 15
0
NCS[n+1] Configuration Register
NCS[n] Configuration Register
Figure 4. Memory Configuration Register
Memory configuration register (MEMCFG1, 2, 3, 4) is a 32-bit read-write register which sets the configuration of
the two expansion and ROM selects. Each select is configured with a two-byte field.
31 30 29
28
27
26 25
24
23
22 20 19
16
Reserved RDON CSCNTL FlashON CLKEN Mem Width BUREN Burst Wait Normal Wait
15 14 13
12
11
10
9
8
7
6
43
0
Reserved RDON CSCNTL FlashON CLKEN Mem Width BUREN Burst Wait Normal Wait
Figure 5. Two-Byte Fields in the Memory Configuration Register for CS[5:0]
(Note : Gray areas are reserved for another feature.)
15 14
13
12
11
10
9
87
6
43
0
Rsv. CSON RDON CSCNTL FlashON CLKEN Mem Width BUREN Burst Wait Normal Wait
Figure 6. Two-Byte Fields in the Memory Configuration Register for CS[6]
31
30
29
28
27
26
25
24 23 22 21
16
LCDON CSON RDON CSCNTL FlashON CLKEN Mem Width Reserved LCD Wait
Figure 7. Two-Byte Fields in the Memory Configuration Register for CS[7]
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