GDC21D601 Datasheet, PDF (160/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
3.6 Test Register 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- -- -- -- -- -- -- -- -- -- -- TCIN1 TCIN0 TREQ1TREQ0 TMEN
Figure 6. Test Register 0
BIT
4
3
2
1
0
Others
INIT. VALUE
0
0
0
0
0
0
Table 4. Test Register 0
NAME
TCIN1
TCIN0
TREQ1
TREQ0
TMEN
DESCRIPTION
Carry-in bit of channel 1 counter
0 : carry-in is not occurred 1 : carry-in is occurred
Carry-in bit of channel 0 counter
0 : carry-in is not occurred 1 : carry-in is occurred
DMAC request bit of channel 1
0 : request is not occurred 1 : request is occurred
DMAC request bit of channel 0
0 : request is not occurred 1 : request is occurred
Test mode enable bit
0 : test mode is not enable 1 : test-mode is enable
Reserved
3.7 Test Register 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TA31 TA30 TA29 TA28 TA27 TA26 TA25 TA24 TA23 TA22 TA21 TA20 TA19 TA18 TA17 TA16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TA15 TA14 TA13 TA12 TA11 TA10 TA9 TA8 TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0
Figure 7. Test Register 1
BIT
31 ~ 0
INIT. VALUE
0
Table 5. Test Register 1
NAME
TA[31:0]
DESCRIPTION
Latches BA[31:0] signal when TMEN bit of Test Register 0 is high
161