GDC21D601 Datasheet, PDF (127/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
DLAB
0
0
x
x
x
x
x
x
x
1
1
P_A[2]
0
0
0
0
0
1
1
1
1
0
0
P_A[1]
0
0
1
1
1
0
0
1
1
0
0
Table 2. Register Address
P_A[0]
0
1
0
0
1
0
1
0
1
0
1
REGISTER
Receiver Buffer(read), Transmitter Holding Register(write)
Interrupt Enable
Interrupt Identification(read)
FIFO Control(write)
Line Control
Modem Control
Line Status
Modem Status
Scratch
Divisor Latch(least significant byte)
Divisor Latch(most significant byte)
Table 3. UART Reset Configuration
REGISTER / SIGNAL
Interrupt Enable Register
Interrupt Identification Register
FIFO Control Register
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register
SOUT
INT_UART (RCVR Errs)
INT_UART (RCVR Data Ready)
INT_UART (THRE)
INT_UART(Modem Status changes)
NRTS
NDTR
REGISTER CONTROL
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Read LSR / RESET
Read RBR / RESET
Read IIR / Write THR / RESET
Read MSR / RESET
Master Reset
Master Reset
REGISTER STATE
0000 0000
0000 0001
0000 0000
0000 0000
0000 0000
0110 0000
xxxx 0000
High
Low
Low
Low
Low
High
High
128