GDC21D601 Datasheet, PDF (185/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
PIO Register (@0xFFFF FC00) -- Continued
ABBREVIATION
PFDR
PFDDR
PGDR
PGDDR
PHDR
PHDDR
PIDR
PIDDR
PJDR
PJDDR
ADDRESS
0xFFFFFC28
0xFFFFFC2C
0xFFFFFC30
0xFFFFFC34
0xFFFFFC38
0xFFFFFC3C
0xFFFFFC40
0xFFFFFC44
0xFFFFFC48
0xFFFFFC4C
DESCRIPTIONS
Port F Data Register
At Power-On default, set as SSPI pins
NIRQOUT when PINMUX_PF[7] = 0
NFIQOUT when PINMUX_PF[6] = 0
BCLKOUT when PINMUX_PF[5] = 0
SCS1 when PINMUX_PF[4] = 0
SCLK1 when PINMUX_PF[3] = 0
SOUT1 when PINMUX_PF[2] = 0
SIN1 when PINMUX_PF[1] = 0
SCS0 when PINMUX_PF[0] = 0
PIOE[7:0] when PINMUX_PF[7:0 ] = 1
PIOE[7:0] when PINMUX_PF[7:0 ] = 1
PIOF[7:0] when PINMUX_PF[7:0 ] = 1
Port F Direction control Register
1: Input Port 0: Output Port
Port G Data Register
At Power-On default, set as DMA pins
RAS1 when PINMUX_PG[7] = 0
RAS0 when PINMUX_PG[6] = 0
DACK1 when PINMUX_PG[5] = 0
DREQ0 when PINMUX_PG[4] = 0
SMDO when PINMUX_PG[3] = 0
SMDI when PINMUX_PG[2] = 0
NRTS when PINMUX_PG[1] = 0
NDTR when PINMUX_PG[0] = 0
PIOG[7:0] when PINMUX_PG[7:0 ] = 1
Port G Direction control Register
1: Input Port 0: Output Port
Port H Data Register
At Power-On default, set as DRAM pins
CAS[3:0] when PINMUX_PH[3:0 ] = 0
PIOH[3:0] when PINMUX_PH[3:0 ] = 1
CS[7:4] when PINMUX_PH[7:4 ] = 0
PIOH[7:4] when PINMUX_PH[7:4 ] = 1
Port H Direction control Register
1: Input Port 0: Output Port
Port I Data Register
At Power-On default, set as DBUS pins
D[23:16] when PINMUX_PI[7:0 ] = 0
PIOI[7:0] when PINMUX_PI[7:0 ] = 1
Port I Direction control Register
1: Input Port 0: Output Port
Port J Data Register
At Power-On default, set as DBUS pins
D[31:24] when PINMUX_PJ[7:0 ] = 0
PIOJ[7:0] when PINMUX_PJ[7:0 ] = 1
Port J Direction control Register
1: Input Port 0: Output Port
R/W INITIAL VALUE
R/W 8b’00000000
R/W 8b’00000000
R/W 8b’00000000
R/W 8b’00000000
R/W 8b’00000000
R/W 8b’00000000
R/W 8b’00000000
R/W ^{8b’00000000}
R/W 8b’00000000
R/W ^{8b’00000000}
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