GDC21D601 Datasheet, PDF (70/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
3. Watchdog Timer Introduction
The GDC21D601 has a one-channel watchdog timer(WDT) for monitoring system operations. If a system becomes
uncontrolled and the timer counter overflows without being rewritten correctly by the CPU, an reset signal is
output to PMU.
When this watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer
operation, an interval timer interrupt is generated at each counter overflow.
The WDT has a clock generator which products eight counter clock sources. The clock signals are obtained by
dividing the frequency of the system clock(B_CLK). Users can select one of eight internal clock sources for input
to the TCNT by CKS2 - CKS0 in the TRCR.
BIT 2 - 0
(CKS2-CKS0)
000
001
010
011
100
101
110
111
Table 2. Internal Counter Clock Sources
CLOCK SOURCE
(SYSTEM CLOCK = 40 MHz)
The system clock is divided by 2
The system clock is divided by 8
The system clock is divided by 32
The system clock is divided by 64
The system clock is divided by 256
The system clock is divided by 512
The system clock is divided by 2048
The system clock is divided by 8192
OVERFLOW INTERVAL
12.8 us
51.2 us
204.8 us
409.6 us
1.64 ms
3.28 ms
13.11 ms
52.43 ms
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