GDC21D601 Datasheet, PDF (182/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

General Purpose Timer Unit Control Register(@0xFFFFF400)
ABBREVIATION
TSTARTR
TSYNCR
TPWMR
TSTINR
TSTOUTR
TSTMODER
TSTINTR
TCONTR0
TIOCR0
ADDRESS
0xFFFFF400
0xFFFFF404
0xFFFFF408
0xFFFFF40C
0xFFFFF410
0xFFFFF414
0xFFFFF418
0xFFFFF420
0xFFFFF424
DESCRIPTIONS
Timer Start Register
Bit 7-6 : Reserved
Bit 5-0 : 1:start counting, 0:stop counting
Timer Sync. Register
Bit 7-6 : Reserved
Bit 5-0 : 1:sync. mode, 0:normal mode
Timer PWM Register(1=PWM,0=normal)
Bit 7-6 : Reserved
Bit 5-0 : 1: PWM mode, 0:normal mode
Timer 0 Control Register
8b’1xx11yyy
xx : mode selection
00 : not cleared-Free running mode
01 : cleared by GRA(periodic mode)
10 : cleared by GRB(periodic mode)
11 : cleared in sync w/ other sync. timer
yyy : timer clock prescaler selection
000 : timer clock = BCLK/2
001 : timer clock = BCLK/4
010 : timer clock = BCLK/16
011 : timer clock = BCLK/64
100 : timer clock = EXT_CLK/2
101 : timer clock = EXT_CLK/4
110 : timer clock = EXT_CLK/64
111 : timer clock = EXT_CLK/2
Timer 0 I/O Control Register
8b’1xxx1yyy
xxx : GRB function select
000 : compare match with no output
001 : output 0 when matched
010 : output 1 when matched
011 : output toggle when matched
100 : GRB input captured at rising edge
101 : GRB input captured at falling edge
110 : GRB input captured at both edge
yyy : GRA function select
000 : compare match with no output
001 : output 0 when matched
010 : output 1 when matched
011 : output toggle when matched
100 : GRA input captured at rising edge
101 : GRA input captured at falling edge
110 : GRA input captured at both edge
GDC21D601
R/W INITIAL VALUE
R/W 8b’11000000
R/W 8b’11000000
R/W 8b’11000000
W
R
W
R
R/W 8b’10011000
R/W 8b’10001000
183