GDC21D601 Datasheet, PDF (146/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Test Register for Input (TIR)
TIR is a 3-bit write-only register defined for test purpose. This register allows simulation of input signals to the
block, as well as the generation of a special test clock signal aimed for production test vectors.
BIT
NAME
2
TNMODE
1
TICUCLK
0
TICSMDI
Table 7. TIR Bit Functions
FUNCTION
Mode select bit
0 : Normal operation mode
1 : Test mode
Programmable serial clock for test
Programmable serial data input for test
Test Register for Output (TOR)
TOR is a 3-bit read-only register defined for test purpose. This register allows simulation of output signals from
the block.
BIT
NAME
2
TSMDO
1
TSMDOEN
0
TSMCLK
Table 8. TOR Bit Functions
FUNCTION
Serial data output line
Serial outputl data enable line
Serial clock line for smart card
The following regitsers are same ones in the UART module. Details on each register see the data sheet of
GDC21D601 UART.
Receiver Buffer Register (RBR)
Transmitter Holding Register (THR)
Interrupt Enable Register (IER)
Interrupt Identification Register (IIR)
FIFO Control Register (FCR)
Line Control Register (LCR)
Line Status Register (LSR)
Scratch Register (SCR)
Divisor Latch (DLL)
Divisor Latch (DLM)
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