GDC21D601 Datasheet, PDF (133/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Line Status Register
This register provides status information to the CPU concerning the data transfer. Table 5. Summary of Registers
shows the contents of the Line Status Register. Details on each bit are :
Bit 0 :
This bit is the receiver Data Ready (DR) indicator. Bit 0 is set to a logic 1 whenever a complete
incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit
0 is reset to a logic 0 by reading all of the data in the Receiver Buffer Register or the FIFO.
Bit 1 :
This bit is the Overrun Error (OE) indicator. Bit 1 indicates that data in the Receiver Buffer Register was
not read by the CPU before the next character was transferred into the Receiver Buffer Register, thereby
destroying the previous character. The OE indicator is set to a logic 1 upon the detection of an overrun
condition, and reset whenever the CPU reads the contents of the Line Status Register. If the FIFO mode
data continues to fill the FIFO beyond the trigger level, an overrun error will occur only after the FIFO is
full and the next character has been completely received in the shift register. OE is indicated to the CPU
as soon as it happens. The character in the shift register is overwritten, but it is not transferred to the
FIFO.
Bit 2 :
This bit is the Parity Error (PE) indicator. Bit 2 indicates that the received data character does not have
the correct even or odd parity, as selected by the even-parity-select bit. The PE bit is set to a logic 1 upon
the detection of a parity error and is reset to a logic 0 whenever the CPU reads the contents of the Line
Status Register. In the FIFO mode this error is associated with the particular character in the FIFO where
it applies to. This error is revealed to the CPU when its associated character is at the top of the FIFO.
Bit 3 :
This bit is the Framing Error (FE) indicator. Bit 3 indicates that the received character did not have a
valid stop bit. Bit 3 is set to a logic 1 whenever the Stop bit following the last data bit or parity bit is
detected as a logic 0 bit (Spacing level). The FE indicator is reset whenever the CPU reads the contents
of the Line Status Register. In the FIFO mode this error is associated with the particular character in the
FIFO where it applies to. This error is revealed to the CPU when its associated character is at the top of
the FIFO. The UART will try to resynchronize after a framing error. To do this, it assumes that the
framing error was due to the next start bit, so it samples this “start” bit twice and then takes it in the
“data”.
Bit 4 :
This bit is the Break Interrupt (BI) indicator. Bit 4 is set to a logic 1 whenever the received data input is
held in the Spacing (logic 0) state for longer than a full word transmission time (that is, the total time of
Start bit + data bits + Parity + Stop bits). The BI indicator is reset whenever the CPU reads the contents
of the Line Status Register. In the FIFO mode this error is associated with the particular character in the
FIFO where it applies to. This error is revealed to the CPU when its associated character is at the top of
the FIFO. When break occurs only one zero character is loaded into the FIFO. The next character
transfer is enabled after SIN goes to the marking state and receives the next valid start bit.
** Note : Bits 1 through 4 are the error conditions that produce a Receiver Line Status interrupt
whenever any of the corresponding conditions is detected and the interrupt is enabled.
Bit 5 :
This bit is the Transmitter Holding Register Empty (THRE) indicator. Bit 5 indicates that the UART is
ready to accept a new character for transmission. In addition, this bit causes the UART to issue an
interrupt to the CPU when the Transmit Holding Register Empty Interrupt enable is set to high. The
THRE bit is set to a logic 1 when a character is transferred from the Transmitter Holding Register into
the Transmitter Shift Register. The bit is reset to logic 0 concurrently with the loading of the Transmitter
Holding Register by the CPU. In the FIFO mode this bit is set when the XMIT FIFO is empty; it is
cleared when at least 1 byte is written to the XMIT FIFO.
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