GDC21D601 Datasheet, PDF (30/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
3. Functional Description
3.1 Introduction
The DRAM controller provides connections allowing a direct interface to up to two banks of DRAM. Each bank is
32/16/8 bits wide and up to 256MB in size. Two RAS lines are provided (one per bank) and four CAS lines (one
per byte line).
3.2 Functional BreakDown
The DRAM controller consists of four main blocks: the Main State Machine & Control Block, the EBI Signal
Control Block, the ASB Interface & Address Generation Block, and the Refresh Timer & Counter Block.
3.3 Main State Machine
This block contains the main DRAM timing control state machine and the decode for the external strobe signals
for the DRAM interface. The state machine generates the timing for the nCAS and nRAS strobes, and the
multiplexing of the DRAM row and column address lines for standard DRAM cycles and refresh cycles. The
nDRAMWE and nDRAMOE signals are asserted appropriately depending on the access type. Word, Half-word,
and Byte accesses are decoded from the lower bits of the BA address bus in order to assert the appropriate nCAS
line(s). For word accesses all four nCAS lines are asserted. Figure 5. Descibes the Main State Machine Diagram.
Local arbitration for refresh cycles is also carried out here as refresh requests are received from the refresh timer
block. The block also supports the self refresh DRAM; enter to and exit from this self refresh state are initiated by
the PDRREQ signal. This is illustrated in Figure 6. DRAM signal timing: power down mode.
RefReq or
!DSEL
!BWRITE
r_IDLE
DSEL
r_WAIT
RAS
BWRITE
r_RnR
CAS
r_RnC1
CAS
r_RnC2
r_RnC3
r_CRWAIT
r_CWWAIT
r_WnR
CAS
r_WnC1
CAS
r_WnC2
r_WnC3
r_RnC4
r_WnC4
Figure 5. Main State Machine Diagram
RefReq or
!DSELD1
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