GDC21D601 Datasheet, PDF (130/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Table 5. Summary of registers gives the details of the UART registers.
Table 5. Summary of Registers
0 DLAB = 0 DLAB = 1 DLAB = 2
0
0
0
Bit Receiver Transmitter Interrupt Interrupt
No. Buffer Holding Enable Ident
Register Register Register Register
RBR
THR
IER
IIR
0 Data Bit 0 Data Bit 0 Enable 0 if
(Note 1)
received interrupt
data
pending
available
interrupt
1 Data Bit 1 Data Bit 1 Enable Interrupt
transmitter ID Bit 0
holding
register
empty
interrupt
2 Data Bit 2 Data Bit 2 Enable Interrupt
receiver ID Bit 1
line status
interrupt
3 Data Bit 3 Data Bit 3 Enable Interrupt
modem ID Bit 2
status (Note 2)
interrupt
4 Data Bit 4 Data Bit 4 0
0
5 Data Bit 5 Data Bit 5 0
0
6 Data Bit 6 Data Bit 6 0
7 Data Bit 7 Data Bit 7 0
FIFO
enabled
(Note 2)
FIFO
enabled
(Note 2)
REGISTER ADDRESS
2
3
4
5
6
7
FIFO
Control
Register
FCR
FIFO
enable
Line
Control
Register
LCR
Word
length
select
Bit 0
MODEM
Control
Register
MCR
Data
Terminal
Ready
(DTR)
Line
MODEM Scratch
Status
Status Register
Register Register
LSR
MSR
SCR
Data Ready Data Clear Bit 0
(DR)
to Send
(DCTS)
RCVR Word
FIFO reset length
select
Bit 1
Request to Overrun
Send
Error
(RTS) (OE)
Delta Data Bit 1
Set Ready
(DDSR)
XMIT Number of
FIFO reset stop bit
Parity
enable
Reserved Even parity Loop
select
Reserved Stick parity 0
RCVR
trigger
(LSB)
RCVR
trigger
(MSB)
Set break 0
Divisor 0
Latch
Access Bit
Parity Error Trailing Bit 2
(PE)
Edge Ring
Indicator
(TERI)
Framing Delta Data Bit 3
Error
Carrier
(FE)
Detect
(DDCD)
Break
Clear to Bit 4
Interrupt Send
(BI)
(CTS)
Transmitter Data Set Bit 5
Holding Ready
Register (DSR)
Empty
(THRE)
Transmitter Ring
Bit 6
Empty Indicator
(TEMT) (RI)
Error in Data
Bit 7
RCVR Carrier
FIFO
Detect
(Note 2) (DCD)
0 DLAB = 1 DLAB
1
=1
Divisor Divisor
Latch
Latch
(LS)
(MS)
DLL
DLM
Bit 0
Bit 8
Bit 1
Bit 9
Bit 2
Bit 10
Bit 3
Bit 11
Bit 4
Bit 12
Bit 5
Bit 13
Bit 6
Bit 14
Bit 7
Bit 15
Note 1 : Bit 0 is the least significant bit seriously transmitted or received.
Note 2 : These bits are always 0 in the GM16C450 mode.
The system programmer may access any of the UART registers summarized in Table 5. Summary of Registers via
the CPU. These registers control UART operation including transmission and reception of data. Each register bit in
the table has its name and reset state as shown.
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