GDC21D601 Datasheet, PDF (55/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

3. Operation Modes
3.1 Introduction
The reset protocol guarantees that the multi-master
system starts up with at most one bus driver enabled
on each shared signal on the bus, and also permits a
protocol reset mechanism for time-out or
‘watchdog’ reset support.
To improve power management, support for a
power-saving mode where bus clocks may be
disabled (or dropped to lower clock) is included.
GDC21D601
The reset and power-down mechanism provides:
• Stable power-up sequence
• Hard Initialization (Power On Reset)
• Soft Initialization (S/W Manual Restart)
Additionally a system bus, once operational,
benefits from well-defined modes of operation:
• RUN in the Standard BUS mode
• RUN in the FAST BUS mode
• Power-down mode
3.2 Reset and Operation Modes
A set of four useful states or modes is defined as
follows:
RESET
When it is power-on, watchdog timer overflow,
watchdog timer manual reset or S/W reset, the MCU
is initialized
Rower on Reset
The most severe form of reset which ensures that no
more than one tri-state driver is enabled on each bus
and initializes all system states to ensure that the
power supply can in fact rise to normal operating
voltage.
This state should be forced by any on-chip power-
on-reset cell or external power-on signal and
maintained until bus clock is safe and stable.
The POR is forced to be in an asynchronous start-up
condition and must be recognized by all master and
slave devices to disable output drives (and wait for a
valid clock)
Manual Reset / Software Reset
The manual reset, which may need to apply to allow
all soft resetting of the bus for a number of clock
cycles. In this reset states the PMU block initializes
all the ASB blocks, Bus controller, DRAM
Controller, DMA Controller, ARM CPU core, and
Arbiter, Decode. However some APB blocks are all
valid in warm reset.
Watchdog Timer Overflow and Manual Reset
The watchdog timer can generate reset signal, when
timer overflows or sets the register value. Detailed
information are in the watchdog timer manual,
please refer to it.
RUN - ARM720T Standard Mode.
The ARM720T works using the FCLK and BCLK.
The FCLK is used for CPU operation clock, and the
B_CLK is used for internal bus access, i.e. AMBA
BUS. So CPU can operate very high frequency. This
mode can control the clock of ASB and APB
devices, so user can disable the clocks of unused
devices or peripherals. It is possible to control the
BCLK or PCLK mask register.
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