GDC21D601 Datasheet, PDF (189/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

I²C Registers (@ 0xFFFF F900 : channel 0)
ABBREVIATION
Baud_r0
CTRL0
Data_r0
Stat_r0
Addr_r0
Test_r0
ADDRESS
0xFFFFF900
0xFFFFF904
0xFFFFF908
0xFFFFF90C
0xFFFFF910
0xFFFFF914
DESCRIPTIONS
I²C Baud rate register for channel 0
I²C Control Register for channel 0
Bit 7-5 : Reserved
Bit 4 : Include address bit
Bit 3 : Transfer END
Bit 2 : Transfer START
Bit 1 : SDA pin set/clear
Bit 0 : Interrupt Enable (0: Disabled)
I²C Data Register for channel 0
I²C Status Register for channel 0
Bit 7-5 : Reserved
Bit 4 : Interrupt Flag bit
Bit 3 : Bus Busy Flag bit
Bit 2 : Bus Lost Flag bit
Bit 1 : SDA pin Ack bit
Bit 0 : Slave Called Flag bit
I²C Address Register for channel 0
Test Register for channel 0
GDC21D601
R/W INITIAL VALUE
W 8b’00000100
W 8b’xxx00010
R/W 8b’xxxxxxxx
R 8b’xxx00000
W 8b’00000000
R/W 8b’00000000
I²C Registers (@0xFFFF FA000 : channel 1)
ABBREVIATION
Baud_r1
CTRL1
Data_r1
Stat_r1
Addr_r1
Test_r1
ADDRESS
0xFFFFFA00
0xFFFFFA04
0xFFFFFA08
0xFFFFFA0C
0xFFFFFA10
0xFFFFFA14
DESCRIPTIONS
I²C Baud rate register for channel 1
I²C Control Register for channel 1
I²C Data Register for channel 1
I²C Status Register for channel 1
I²C Address Register for channel 1
Test Register for channel 1
R/W INITIAL VALUE
W 8b’10011000
W 8b’10011000
R/W 8b’10011000
R 8b’10011000
W 8b’10011000
R/W 8b’10011000
I²C Registers (@ 0xFFFF FB00 : channel 2)
ABBREVIATION
Baud_r2
CTRL2
Data_r2
Stat_r2
Addr_r2
Test_r2
ADDRESS
0xFFFFFB00
0xFFFFFB04
0xFFFFFB08
0xFFFFFB0C
0xFFFFFB10
0xFFFFFB14
DESCRIPTIONS
I²C Baud rate register for channel 2
I²C Control Register for channel 2
I²C Data Register for channel 2
I²C Status Register for channel 2
I²C Address Register for channel 2
Test Register for channel 2
R/W INITIAL VALUE
W 8b’10011000
W 8b’10011000
R/W 8b’10011000
R 8b’10011000
W 8b’10011000
R/W 8b’10011000
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