GDC21D601 Datasheet, PDF (83/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
3. Interrupt Controller
3.1 Introduction
The interrupt controller provides a interface between multiple interrupt source and the processor. The interrupt
controller supports internal and external interrupt sources. Internally there are 19 peripheral interrupt sources.
Externally there are 6 interrupt sources. Therefore certain interrupt bits can be defined for the basic functionality
required in any system, while the remaining bits are available for use by other devices in any particular
implementation.
INT #
INT 0
INT 1
INT 2
INT 3
INT 4
INT 5
INT 6
INT 7
INT 8
INT 9
INT 10
INT 11
INT 12
INT 13
INT 14
INT 15
INT 16
INT 17
INT 18
INT 19
INT 20
INT 21
INT 22
INT 23
INT 24
INT 25
Table 2. Interrupt Controller Default Setting Value
EXTERNAL INT0
EXTERNAL INT1
EXTERNAL INT2
EXTERNAL INT3
EXTERNAL INT4
EXTERNAL INT5
COM TX
COM RX
DMA
RTC
WDT
I²C0
I²C1
I²C2
UART0
UART1
Smart Card Interface
SSI CHA
SSI CHB
TIMER CHA
TIMER CHB
TIMER CHC
TIMER CHD
TIMER CHE
TIMER CHF
Software Interrupt
INTERRUPT SOURCE
The Users can set the active mode of all interrupt source inputs. The default mode is the falling-edge trigger mode.
Any inversion or latching required to provide edge sensitivity must be provided at the generating source of the
interrupt.
No hardware priority scheme or any form of interrupt vectoring is provided, but the priority can be determined
using FIQ mask register and IRQ mask register under software control.
FIQ mask register and IRQ mask register are also provided to generate an interrupt under software control.
Typically these registers may be used to determine either a FIQ interrupt or an IRQ interrupt.
84