GDC21D601 Datasheet, PDF (42/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
3. Functional Description
The Static Memory Controller has following functions:
• memory bank select
• off-chip expansion clock driver
• wait states generation
• byte lane write control
• burst read access
• various type control signal generation
These are described below.
3.1 Memory Bank Select
The chip select signal generation is controlled by BA[26:24]. From Table 3 static memory bank select coding is
shown that these signals coded to CS[7:6] and nCS[5:0].
DSEL
1
1
1
1
1
1
1
1
Table 3. Static Memory Bank Select Coding (MODE R)
BA[26:24]
000
001
010
011
100
101
110
111
CS[7:6]
00
00
00
00
00
00
01
10
nCS[5:0]
111110
111101
111011
110111
101111
011111
111111
111111
MEMORY CONFIGURATION
nCS0 configuration
nCS0 configuration
nCS2 configuration
nCS3 configuration
nCS4 configuration
nCS5 configuration
CS6 configuration
CS7 configuration
3.2 Off-Chip Expansion Clock Driver
In the Static Memory Controller, the system clock input BCLK is passed directly to EXPCLK during memory
cycles if the expansion clock enable bit of the corresponding memory bank configuration is set.
3.3 Access Sequencing
Bank configuration also determines the width of the external memory devices. When the external memory bus is
narrower than the transfer initiated from the current master, the internal transfer will take several external bus
transfers to complete. For example, in case that bank zero is configured as 8-bit wide memory and a 32-bit read is
initiated, the ASB bus will stall while the SRAM Controller reads four consecutive bytes from the memory. During
these accesses the data path is controlled (using the MemByteSeq[1:0] signals) to de-multiplex these four bytes
into one 32-bit word on the ASB bus.
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