GDC21D601 Datasheet, PDF (101/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
5. General Purpose Timer Unit Memory Map
The base address of the general-purpose timer unit is 0xFFFFF400 and the offset of any particular register from the
base address is fixed.
Table 2. General Purpose Timer Unit Register Memory Map
ADDRESS
Gptu Base + 0x00
Gptu Base + 0x04
Gptu Base + 0x08
Gptu Base + 0x0C
Gptu Base + 0x10
Gptu Base + 0x14
Gptu Base + 0x18
Gptu Base + 0x20
Gptu Base + 0x24
Gptu Base + 0x28
Gptu Base + 0x2C
Gptu Base + 0x30
Gptu Base + 0x34
Gptu Base + 0x38
Gptu Base + 0x40
Gptu Base + 0x44
Gptu Base + 0x48
Gptu Base + 0x4C
Gptu Base + 0x50
Gptu Base + 0x54
Gptu Base + 0x58
Gptu Base + 0x60
Gptu Base + 0x64
Gptu Base + 0x68
Gptu Base + 0x6C
Gptu Base + 0x70
Gptu Base + 0x74
Gptu Base + 0x78
Gptu Base + 0x80
Gptu Base + 0x84
Gptu Base + 0x88
Gptu Base + 0x8C
Gptu Base + 0x90
Gptu Base + 0x94
Gptu Base + 0x98
Gptu Base + 0xA0
Gptu Base + 0xA4
Gptu Base + 0xA8
Gptu Base + 0xAC
Gptu Base + 0xB0
Gptu Base + 0xB4
Gptu Base + 0xB8
READ LOCATION
TSTARTR
TSYNCR
TPWMR
TSTOUTR
TSTINTR
TCONTR0
TIOCR0
TIER0
TSTATUSR0
TCOUNT0
GRA0
GRB0
TCONTR1
TIOCR1
TIER1
TSTATUSR1
TCOUNT1
GRA1
GRB1
TCONTR2
TIOCR2
TIER2
TSTATUSR2
TCOUNT2
GRA2
GRB2
TCONTR3
TIOCR3
TIER3
TSTATUSR3
TCOUNT3
GRA3
GRB3
TCONTR4
TIOCR4
TIER4
TSTATUSR4
TCOUNT4
GRA4
GRB4
WRITE LOCATION
TSTARTR
TSYNCR
TPWMR
TSTINR
TSTMODER
TCONTR0
TIOCR0
TIER0
TCOUNT0
GRA0
GRB0
TCONTR1
TIOCR1
TIER1
TCOUNT1
GRA1
GRB1
TCONTR2
TIOCR2
TIER2
TCOUNT2
GRA2
GRB2
TCONTR3
TIOCR3
TIER3
TCOUNT3
GRA3
GRB3
TCONTR4
TIOCR4
TIER4
TCOUNT4
GRA4
GRB4
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