GDC21D601 Datasheet, PDF (171/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

DRAM Controller Registers(@0xFFFFED00)
ABBREVIATION
DRAMRCR
DRAMconCPU
DRAMCDMA
ADDRESS
0xFFFFED00
0xFFFFED04
0xFFFFED08
DESCRIPTIONS
DRAM Refresh Control Register
Bit 15-8: REFCNT
(DRAM Refresh Clock Divisor)
RefClock = BCLK / REFCNT
Bit 7 : DRAM Refresh clock control
0 / 1 = Disabled / Enabled
Bit 6-0 : REFDIV(DRAM Refresh rate)
Frequency (KHz)
= 2*[RefClock /(RFDIV + 1)]
DRAM Controller for CPU
Bit 15-7: Reserved
Bit 6: DMAEn(DMA Control signal )
0 / 1 = DMA Disabled / Enabled
Bit 5: TRP( t_rp = |RAS-CAS| )
Bit 4 : TCP(t_cp= |Low phase of CAS|)
Bit 3-2: Wait count
00: 0-wait
01: 1-wait
10: 2-wait
11: 3-wait
Bit 1-0: Bank size
00 : byte
01 : Half-word
10 : Word
11 : Reserved
DRAM Controller for DMA
Bit 15-6: Reserved
Bit 5: TRP( t_rp = |RAS-CAS| )
Bit 4 : TCP(t_cp= |Low phase of CAS|)
Bit 3-2: Wait count
00: 0-wait
01: 1-wait
10: 2-wait
11: 3-wait
Bit 1-0: Bank size
00 : byte
01 : Half-word
10 : Word
11 : Reserved
GDC21D601
R/W INITIAL VALUE
W
16h’0000
R/W 7b’0000000
R/W 6b’000000
172