GDC21D601 Datasheet, PDF (158/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
3. Programmer’ s Model
3.1 Memory Map
The base addresses for the DMAC’s registers are not fixed and may be different for any particular system
implementation. The base address of the DMAC’s register is 0xFFFFEE00. However, the offset of any particular
DMAC’s register from the base address is fixed.
Table 2. External Signal Descriptions
ABBREVIATION
ADDR.
OFFSET
NAME
R/W
SAR0
H’00 Source Address Register for Channel 0
R/W
DAR0
H’04 Destination Address Register for Channel 0
R/W
TNR0
H’08 Transfer Number Register for Channel 0
R/W
CCR0
H’0C Channel Control Register for Channel 0
R/W
SAR1
H’10 Source Address Register for Channel 1
R/W
DAR
H’14 Destination Address Register for Channel 1
R/W
TNR1
H’18 Transfer Number Register for Channel 1
R/W
CCR1
H’1C Channel Control Register for channel 1
R/W
TSTR0
H’20 Test Register 0
R/W
TSTR1
H’24 Test Register 1
R
TSTR2
H’28 Test Register 2
R
DMAOR
H’2C DMA Operation Register
R/W
INITIAL
VALUE
H’00000000
H’00000000
H’00001111
H’00000000
H’00000000
H’00000000
H’00001111
H’00000000
H’00000000
H’00000000
H’00000000
H’00000000
3.2 Source Address Register 0,1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAB31 SAB30 SAB29 SAB28 SAB27 SAB26 SAB25 SAB24 SAB23 SAB22 SAB21 SAB20 SAB19 SAB18 SAB17 SAB16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAB15 SAB14 SAB13 SAB12 SAB11 SAB10 SAB9 SAB8 SAB7 SAB6 SAB5 SAB4 SAB3 SAB2 SAB1 SAB0
Figure 2. Source Address Register
3.3 Destination Address Register 0, 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAB31DAB30DAB29 DAB28DAB27DAB26 DAB25DAB24DAB23DAB22DAB21DAB20DAB19DAB18DAB17DAB16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAB15DAB14DAB13 DAB12DAB11DAB10 DAB9 DAB8 DAB7 DAB6 DAB5 DAB4 DAB3 DAB2 DAB1 DAB0
Figure 3. Destination Address Register
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