GDC21D601 Datasheet, PDF (85/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
4. Interrupt Controller Memory Map
The base address of the interrupt controller is 0xFFFF F200. The offset of any particular register from the base
address is fixed.
Table 3. Memory Map of the Interrupt Controller APB Peripheral
ADDRESS
IntBase + 0x000
IntBase + 0x004
IntBase + 0x008
IntBase + 0x00C
IntBase + 0x010
IntBase + 0x014
IntBase + 0x018
IntBase + 0x01C
IntBase + 0x020
IntBase + 0x024
IntBase + 0x028
READ LOCATION
Mask Register
Trigger Mode Register
Trigger Polarity Register
Direction Register
FIQ Status Register (Read-only)
IRQ Status Register (Read-only)
FIQ Mask Register
IRQ Mask Register
TicOutputRegister
WRITE LOCATION
Mask Register
Trigger Mode Register
Trigger Polarity Register
Direction Register
FIQ Mask Register
IRQ Mask Register
Status Clear Register (Write-only)
TicInput Register
86