GDC21D601 Datasheet, PDF (54/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
2. Hardware Interface and Signal Description
The PMU block is connected to the APB bus. Table 1. describes the APB signals and clock signals used and
produced.
NAME
nPOR
INT_REQ_IN
WD_OF_IN
MAN_RST_IN
P_D[15:0]
P_A[7:0]
P_WRITE
P_STB
P_SEL
SCLK_IN
PCLK_IN
Tfclk
Tbclk
BCLK_XXX
PCLK_XXX
FCLK
FASTBUS
NPDM
REMAP
WD_OF_OUT
B_RESETn
P_RESETn0
P_RESETn1
RESETn_OUT
TYPE
I
I
I
I
I/O
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
Table 1. PMU Signal Descriptions
DESCRIPTION
External reset input.
Interrupt request signal from the interrupt controller.
Watch dog timer overflow signal.
S/W manual reset pin from watch dog timer.
This is the bi-directional peripheral data bus. This block drives the data bus
during read cycle, when P_WRITE is LOW.
This is the peripheral address bus, which uses individual peripheral for decoding
register accesses to that peripheral. The addresses become valid before PSTB goes
to HIGH and remain valid after PSTB goes to LOW.
This signal indicates a write to a peripheral when it is HIGH and a read from a
peripheral when LOW.
It has the same timing as the peripheral address bus.
This strobe signal is used to time all accesses on the peripheral bus. The falling
edge of PSTB is coincident with the falling edge of BCLK
When HIGH, this signal indicates that module has been selected by the APB
bridge.
System clock input . This is the clock input from external clock circuit .
UART clock. This is the clock input from external UART clock module.
When it is in TIC test mode, this s the FCLK clock input signal. When TSTCR[1]
is set to 1(HIGH) for entering TIC test mode.
When it is in TIC test mode, BCLK clocks signal. First set the TSTCR[1] to 1 for
entering TIC test mode.
System Bus clock is generated from SCLK_IN. All ASB block and some APB
blocks are operated by this clock.
APB Peripheral Bus Clocks. All APB blocks are operated by the clocks.
FCLK pin for ARM720T. It is used in standard mode, when FASTBUS is LOW.
ARM720T bus mode control signal. When it is LOW, it is in standard bus mode.
When HIGH, fast bus mode.
Indicates the PDM mode of PMU. When it is LOW, MCU entered in power down
mode. When HIGH, normal operation mode.
Indicates that the reset memory map is in operation.
Watch dog overflow output signal for external devices.
Reset signal for ASB devices
Reset signal for APB devices
Same as P_RESETn0, but in manual reset mode this is not asserted.
Reset signal for external devices.
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