GDC21D601 Datasheet, PDF (106/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Timer Status Register (TSTATUSR)
Eight-bit readable register contains the flags that indicate TCOUNT overflow/underflow and GRA/GRB compare
match or input capture. This flags are interrupt sources.
BIT
7 (reserved)
6 (reserved)
5 (reserved)
4 (reserved)
3 (reserved)
2 (OVFI)
1 (MCIB)
0 (MCIA)
INITIAL
VALUE
1
1
1
1
1
0
0
0
Table 9. TIER Bit Description
FUNCTION
0 = clear condition
1 = setting condition
indicate TCOUNT overflow/underflow
indicate a GRB compare match or
input capture
indicate a GRA compare match or
input capture
Timer Counter (TCOUNT)
16-bit readable and writable counter. The clock source is selected by TCONTR of each channel. TCOUNT is
cleared to 0x0000 by compare match with the corresponding GRA or GRB, or by input capture to GRA or GRB.
When TCOUNT is overflow or underflow, OVFI in the TSTATUSR is set to ‘1’.
TCNT0 (16 bit) : upcounter
TCNT1 (16 bit) : upcounter
TCNT2 (16 bit) : upcounter
TCNT0 (16 bit) : upcounter
TCNT0 (16 bit) : upcounter
TCNT0 (16 bit) : upcounter
General Register A, B (GRA, GRB)
16-bit readable and writable register. There are 2 general registers for each channel (total 12). Each general register
can function as either an output compare register or an input capture register by setting it in the TIOCR.
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