GDC21D601 Datasheet, PDF (45/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

LCDON
CSON
RDON
CSCNTL
FlashON
CLKEN
BUREN
GDC21D601
LCD enable. When the Bank 7 is connected to LCD panel for text display, setting this bit
enables LCD wait to access directly LCD device. LCD wait bit is 6 bits therefore wait cycle
is from 1 to 64.
nCS enable. Setting this bit is enables the CS6 and CS7 to be active low signal from active
high signal that supports various devices.
select the polarity of EXPRDY. When this bit is set to 0, EXPRDY signal act as positive
active signal. When this bit is set to 1, EXPRDY signal act as negative active signal.
Make the control signals (Address, Data, CS, RnW, etc.) of external device to be similar
Motorolar type CPU.
Flash memory enable. When this bit is set to 1, memory control signals, nCS, nWEN[1:0],
and nSRAMOE, are adjusted to flash memory control signal timing.
Expansion clock enable. Setting this bit enables the EXPCLK to be active during accesses to
the specified bank. This provides a timing reference for devices that need to extend bus
cycles using the EXPRDY input. Back to back sequential accesses result in a continuous
clock.
Burst enable. Setting this bit enables burst reads to take advantage of faster access time from
ROM devices that support burst mode.
Note
Banks using EXPCLK and EXPRDY for off-chip peripheral control should not enable burst mode, and
should be designed and set up to use a specific number of wait states in each access. The peripheral
should time the access by counting EXPCLK cycles (there is no explicit indication of access start or
end) and determine the access direction and width by using nWEN[3:0].
Table 6. Values of the Mem Width Field Define the Bus Width Field.
Table 6. Values of the Mem Width Field
MEM WIDTH FIELD
00
01
10
11
EXPANSION TRANSFER MODE
32-bit wide bus access
16-bit wide bus access
8-bit wide bus access
Reserved
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