GDC21D601 Datasheet, PDF (161/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

3.8 Test Register 2
GDC21D601
Bit 15 14 13 12 11 10 9 8 7 6 5
4
3
2
1
0
-- -- -- -- -- -- -- -- -- -- BTRAN1 BTRAN0 BSIZE1 BSIZE0 AREQ BWRITE
Figure 8. Test Register 2
BIT
5~4
3~2
1
0
Others
INIT. VALUE
00
00
0
0
0
Table 6. Test Register 2
NAME
DESCRIPTION
BTRAN[1:0] Latches BTRAN signal
BSIZE[1:0]
AREQ
BWRITE
Latches BSIZE signal
Latches AREQ signal
Latches BWRITE signal
Reserved
3.9 DMA Operation Register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- -- -- -- -- -- -- -- -- -- -- -- -- -- PRIOM DMAEN
Figure 9. DMA Operation Register
BIT
1
0
Others
INIT. VALUE
0
0
0
Table 7. DMA Operation Register
NAME
PRIOM
DMAEN
DESCRIPTION
Channel priority level selection bit
0 : Ch0 > Ch1
1 : Ch1 > Ch0
DMAC operation enable bit
0 : DMAC is not enabled 1 : DMAC is enabled
Reserved
162