GDC21D601 Datasheet, PDF (137/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
MODEM Control Register
This register controls the interface with the MODEM or data set (or a peripheral device emulating a MODEM).
The contents of the MODEM Control Register are indicated in Table 5. Summary of Registers, and are described
below.
Bit 0 :
This bit controls the Data Terminal Ready (NDTR) output. When this bit is set to a logic 1, the NDTR
output is forced to be a logic 0. When bit 0 is reset to a logic 0, the NDTR output is forced to be a logic
1.
** Note : The NDTR output of the UART may be applied to an EIA inverting line driver (such as the
DS1488) to obtain the proper polarity input at the succeeding MODEM or data set.
Bit 1 : This bit controls the Request to Send (NRTS) output. Bit 1 affects the NRTS output in an identical
manner that described above for bit 0.
Bit 2 : Not used
Bit 3 : Not used
Bit 4 :
This bit provides a local loopback feature for diagnostic testing of the UART. When bit 4 is set to logic 1,
the transmitter Serial Output (SOUT) is set to the Marking (logic 1) state. The receiver Serial Input (SIN)
is disconnected; the output of the Transmitter Shift Register is “looped back” into the Receiver Shift
Register input. The four MODEM Control inputs (NCTS, NDSR, NDCD, and NRI) are disconnected.
The two MODEM Control outputs (NDTR and NRTS) and two internal nodes (OUT1 and OUT2) are
internally connected to the four MODEM Control inputs and the MODEM Control output pins are
forced to be their inactive state (high). On the diagnostic mode, the transmitted data is immediately
received. This feature allows the processor to verify the transmit- and received-data paths of the UART.
In the diagnostic mode, the receiver and transmitter interrupts are fully operational. Their sources are
external to the part. The MODEM Control interrupts are also operational, but the interrupts sources are
now the lower four bits of the MODEM Control Register instead of the four MODEM Control inputs.
The interrupts are still controlled by the Interrupt Enable Register.
Bit 5 through 7 :These bits are permanently set to logic 0.
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