GDC21D601 Datasheet, PDF (115/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
4. Functional Description
All block registers are cleared during power on reset (BnRES LOW).
This disables the output drivers for port A, C, E, G and I (input as default) and enables the drivers for port B, D, F,
H, and J (output as default).
For each port there is a Data Register and a Data Direction Register. On reads, the Data Register contains the
current status of correspondent port pins whether they are configured as input or output. Writing to a Data Register
only affects the pins that are configured as outputs.
The Data Direction Registers operates in a different manner on each port:
• For every port, a “0” in the data direction register indicates the port is defined as an output (default), a “1” in the
data direction register indicates the port is defined as an input.
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