GDC21D601 Datasheet, PDF (186/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

SSPI Register (@ 0xFFFF F800)
ABBREVIATION
SSCR0A
ADDRESS
0xFFFFF800
SSCR0B
0xFFFFF804
SSDR0
SSSR0
0xFFFFF808
0xFFFFF80C
SSTR0
SSCR1A
0xFFFFF810
0xFFFFF820
SSCR1B
0xFFFFF824
DESCRIPTIONS
SSPI 0 Control Register A
Bit 7 : Enters Test mode when set to 0
Bit 6 : CS is Active High when set to 0
Bit 5 : SSPI 0 Disabled when set to 0
Bit 4 : Slave mode when set to 0
Bit 3 : LSB input first when set to 0
Bit 2 : LSB out first when set to 0
Bit 1 : Rising edge clock when set to 0
Bit 0 : Slave: CS disabled when set to 0
SSPI 0 Control Register B
Bit 7 : Tx interrupt enabled when set to 1
Bit 6 : Tx FIFO empty interrupt enable
Bit 5 : Rx FIFO full interrupt enable
Bit 4 : Tx FIFO full interrupt enable
Bit 3 : Rx FIFO enabled when set to 1
Bit 2 : Tx FIFO enabled when set to 1
Bit 1 : Rising edge clock when set to 0
Bit 0 : Slave: CS disabled when set to 0
SSPI 0 Data Register
SSPI 0 Status Register
Bit 7 : Rx FIFO Empty
Bit 6 : Tx FIFO Empty
Bit 5 : Rx FIFO FULL
Bit 4 : Tx FIFO FULL
Bit 3 : Tx END
Bit 2 : Reserved
Bit 1 : Reserved
Bit 0 : SSPI BUSY
SSPI 0 Term Register
SSPI 1 Control Register A
Bit 7 : Enters Test mode when set to 0
Bit 6 : CS is Active High when set to 0
Bit 5 : SSPI 0 Disabled when set to 0
Bit 4 : Slave mode when set to 0
Bit 3 : LSB input first when set to 0
Bit 2 : LSB out first when set to 0
Bit 1 : Rising edge clock when set to 0
Bit 0 : Slave: CS disabled when set to 0
SSPI 1 Control Register B
Bit 7 : Tx interrupt enabled when set to 1
Bit 6 : Tx FIFO empty interrupt enable
Bit 5 : Rx FIFO full interrupt enable
Bit 4 : Tx FIFO full interrupt enable
Bit 3 : Rx FIFO enabled when set to 1
Bit 2 : Tx FIFO enabled when set to 1
Bit 1 : Rising edge clock when set to 0
Bit 0 : Slave: CS disabled when set to 0
GDC21D601
R/W INITIAL VALUE
R/W 8b’11111111
1: Normal
1: Active Low
1: Enabled
1: Master
1: MSB in
1: MSB out
1: Falling
1: CS enabled
R/W 8b’00000000
0: Disable
0: Disable
0: Enabled
0: Master
0: MSB in
0: MSB out
0: Falling
0: CS enabled
R/W 8b’11111111
R 8b’00000000
W 8b’11111111
R/W 8b’11111111
1: Normal
1: Active Low
1: Enabled
1: Master
1: MSB in
1: MSB out
1: Falling
1: CS enabled
R/W 8b’00000000
0: Disable
0: Disable
0: Enabled
0: Master
0: MSB in
0: MSB out
0: Falling
0: CS enabled
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