GDC21D601 Datasheet, PDF (43/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
3.4 Wait State Generation
The Static Memory Controller supports wait states for read and write accesses. This is configurable between one
and 16 wait states for standard memory access and zero and 15 wait states for burst mode reads from ROMs.
Note
Wait state control refers to external transfer wait states. The number of cycles where an AMBA transfer completes
is controlled by two other factors; access width and external memory width. The Static Memory Controller also
allows transfers to be extended indefinitely, by asserting EXPRDY to LOW. To hold the current transfer EXPRDY
must be asserted on the falling edge of BCLK before the last cycle of the access. The transfer cannot be completed
until EXPRDY is HIGH for at least one cycle.
3.5 Burst Read Control
This supports sequential access burst reads of up to four consecutive locations in 8-, 16- or 32-bit memories. This
feature supports burst mode ROM devices and increases the bandwidth by using a reduced (configurable) access
time for three sequential reads following a quad-location boundary read. (Note that quad-location boundaries occur
when A[1:0]=00 for byte wide memories.)
3.6 Byte Lane Write Control
This controls nWEN[1:0] according to AMBA transfer width (indicated by BSIZE[1:0]), external memory width,
BA[1:0], and the access sequencing. The following table shows the basic coding assuming 32-bit external memory:
BSIZE[1:0]
10 (word)
01 (half-word)
01 (half-word)
00 (byte)
00 (byte)
00 (byte)
00 (byte)
Table 4. nWEN Coding
BA[1:0]
XX
1X
0X
11
10
01
00
nWEN[3:0]
0000
0011
1100
0111
1011
1101
1110
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