GDC21D601 Datasheet, PDF (57/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
4. Register Description
The PMU supplies the clock to all of the blocks in the MCU.
4.1 PMU Control Register
This register controls the operation mode of PMU. When power on reset states, register value is initialized by Run
State (00). The address of register is PMU_BASE(=0xFFFF F000) + 0x00h.
BIT
INITIAL
7~0
0x0
Table 2. PMUCR Bit Functions
NAME
PMUCR
FUNCTION
0x0 - Clear PMU Status Register.
0x03 – Entering the PD(Power down) Mode
the other values - None effect.
4.2 PMU Status Register
This register holds the previous status and reset state of PMU. The address of register is PMU_BASE + 0x00h.
Table 3. PMUSR Bit Functions
BIT
INITIAL
NAME
FUNCTION
5, 4
00
PMUST[5:4]
00 - The Power-On reset state (nPOR).
Previous Reset
01 - S/W Reset state using PMU.
Status bits
10 - S/W Manual reset state using WDT.
11 - WD overflow reset state using WDT.
3, 2
00
PMUST[3:2]
00 - Running (FAST, SLOW) after nPOR.
Current Status bits 01 - Running (FAST, SLOW) after WD_OF.
10 - Running (FAST, SLOW) after Man_reset
1, 0
00
PMUST[1:0]
00 - Start (FAST, SLOW) after nPOR.
Previous Status 01 - Start (FAST, SLOW) after WD_OF.
bits
10 - Start (FAST, SLOW) after Man_reset
11 - Start (FAST, SLOW) after PD Mode.
4.3 REMAP Register
The REMAP register controls re-mapping operation when the reset (POR or MAN_RST) signal is asserted or S/W
is reset by RSTCR. The address is PMU_BASE + 0x10h.
BIT
INITIAL
0
0
Table 4. REMAP Bit Functions
NAME
REMAP
FUNCTION
0 – Reset operation mode map
1 – Normal operation mode map
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