GDC21D601 Datasheet, PDF (71/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
4. Watchdog Timer Operation
The Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/nIT and TMEN bits of the TRCR to 1. Software must prevent
TCNT overflow by rewriting the TCNT value(normally by writing 0x00) before overflow occurs. If the TCNT fails
to be rewritten and overflow due to a system crash or the like, INT_WDT signal and PORESET/MNRESET signal
are output. The INT_WDT signal is not output if INTEN is disabled (INTEN = 0).
TCNT
value
OxFF
W T /nIT = 1
Ox00
TMEN = 1
0x00 written in
TCNT
WTOVF = 1
FAULT and internal reset generated
tim e
Figure 4. Operation in the Watchdog Timer Mode
If the RSTEN bit in the TRCR is set to 1, a signal to reset the chip will be generated internally when TCNT
overflows. Either a power-on reset or a manual reset can be selected by the RSTSEL bit.
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