GDC21D601 Datasheet, PDF (81/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
2. Hardware Interface and Signal Description
The Interrupt Controller module is connected to the APB bus.
Table 1. APB Signal Descriptions
NAME
TYPE
SOURCE/
DESTINATION
DESCRIPTION
P_A[5:2]
I APB Bridge
This is the peripheral address bus, which is used by an individual
peripheral for decoding register accesses to that peripheral.
The addresses become valid before P_STB goes to HIGH and
remain valid after P_STB goes to LOW.
P_D[26:0]
I/O APB Peripherals, This is the bidirectional peripheral data bus. The data bus is driven
B_D bus
by this block during read cycles (when P_WRITE is LOW).
P_STB
I APB Bridge
This strobe signal is used to time all accesses on the peripheral
bus. The falling edge of P_STB is coincident with the falling edge
of B_CLK.
P_WRITE
I APB Bridge
When this signal is HIGH, it indicates a write to a peripheral.
When this signal is LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before P_STB goes to HIGH and remains valid after
P_STB goes to LOW.
P_SEL
I APB Bridge
When this signal is HIGH, it indicates that this module has been
selected by the APB bridge. This selection is a decode of the
system address bus (ASB). See AMBA Peripheral Bus Controller
(ARM DDI - 0044) for more details.
INTESource[25:0] I APB peripherals/ FIQ/IRQ interrupt signals into the Interrupt module. These active
external world HIGH signals indicate that interrupt requests have been generated
(IRQESource[25] is internally generated in the Interrupt Controller
module and used to provide a software triggered IRQ).
NFIQ
O ARM CORE
NFIQ interrupt input to the ARM core.
NIRQ
O ARM CORE
NIRQ interrupt input to the ARM core.
BnRES
I PMU
Reset signal generated from the Power Management Unit.
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