GDC21D601 Datasheet, PDF (67/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Section 9. Watchdog Timer
1. General Description
The watchdog timer has:
• watchdog timer mode and interval timer mode
• interrupt signal INT_WDT to interrupt controller in the watchdog timer mode & interval timer mode
• output signal PORESET and MNRESET to PMU(Power Management Unit)
• eight counter clock sources
• selection whether to reset the chip internally or not
• two types of reset signal : power-on reset and manual reset
System clock
Clock
Generation
Clock
Selection
INT_WDT
PORST
MNRST
Reset
Control
Interrupt
Control
Control logic
Overflow
clock
RSTSR
TCNT
TRCR
Module data bus
TCNT : Timer Counter (8bit)
TRCR : Timer/Reset Control Register (8bit)
RSTSR : Reset Status Register (2bit)
Figure 1. Watchdog Timer Module Block Diagram
Internal
data bus
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